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Introduction | 집적회로 공정이란 무엇인가 | ![]() |
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집적회로공정 개요 | 집적회로 공정에 대한 전반적인 설명 | ![]() |
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집적회로공정 개요 | 집적회로 공정에 대한 전반적인 설명 | ![]() |
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반도체 공학기초 | 1. Dopants 2. Calculation of carrier concentration 3. Mobility and resistance | ![]() |
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반도체 공학기초 | 1. Sheet resistance (Rs) 2. Local oxidation of silicon (LOCOS) | ![]() |
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Isolation과 contact issue | 1. Isolation methods 2. Contacts 3. Process flow of MOSFETs | ![]() |
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Isolation methods | 1. Local oxidation of silicon (LOCOS) 2. Shallow trench isolation (STI) 3. Thermal oxidation | ![]() |
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Oxidation | 1. Thermal oxidation 2. Properties of thermal SiO2 3. Modeling of thermal oxidation | ![]() |
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Oxidation | 1. Modeling of thermal oxidation 2. Effect of impurities 3. Dopant redistribution | ![]() |
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Oxidation | Oxide charges | ![]() |
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Oxidation | 1. Oxidation recipe 2. Oxidation source/method | ![]() |
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Ion implantation | 1. Ion implantation 2. Concentration and dose 3. Energy loss mechanism | ![]() |
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Ion implantation | 1. Dose vs. concentration 2. Junction depth 3. Sheet resistance of ion implanted layer 4. Ion channeling | ![]() |
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Ion implantation | 1. Ion channeling 2. Implantation damage 3. Dopant activation | ![]() |
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Diffusion | 1. Dopant diffusion 2. Diffusion mechanisms in Si 3. Diffusion process modeling | ![]() |
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Diffusion | 1. High concentration diffusion effect 2. Oxidation enhanced diffusion (OED) 3. Sheet resistance | ![]() |
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Gate stack | 1. Gate leakage current 2. Tunneling mechanisms 3. Evaluation of gate dielectric thickness 4. Equivalent oxide thickness (EOT) 5. High-k gate dielectric | ![]() |
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Gate stack | 1. Gate leakage current 2. Tunneling mechanisms 3. Evaluation of gate dielectric thickness 4. Equivalent oxide thickness (EOT) 5. High-k gate dielectric | ![]() |
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Photolithography | 1. Photolithography 2. Photomask layout 3. Photoresist / lift-off 4. Theory of photolithography | ![]() |
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Metallization | 1. Interconnection RC time delay 2. Contact resistance 3. Aluminum metallization | ![]() |
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Metallization | 1. Problems of aluminum metallization 2. Silicide process 3. Surface planarization 4. Damascene process | ![]() |
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Metallization/Scaling of CMOS | 1. Self-aligned source and drain 2. Lightly doped drain (LDD) 3. Salicide process 4. Scaling trend of CMOS | ![]() |